Table of Contents
Advertisement
Reset and clock control (RCC) for STM32F412xx
6.3.11
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: RNG clock enable
Set and cleared by software.
0: RNG clock disabled
1: RNG clock enabled
Bits 5:0 Reserved, always read as 0.
140/1163
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
OTGFS
RNG
Res.
Res.
EN
EN
rw
rw
RM0402 Rev 6
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
RM0402
17
16
Res.
Res.
1
0
Res.
Res.
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32F412 and is the answer not in the manual?
Questions and answers