Parity Control; Table 152. Frame Formats; Figure 253. Mute Mode Using Address Mark Detection - ST STM32F412 Reference Manual

RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver
In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RX
RWU
25.4.7

Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in
M bit
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
Even parity
The parity bit is calculated to obtain an even number of "1s" inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in
USART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software

Figure 253. Mute mode using address mark detection

IDLE Addr=0 Data 1 Data 2
MMRQ written to 1
(RXNE was cleared)
Non-matching address
PCE bit
0 0
0 1
1 0
1 1
IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5
Mute mode
Matching address

Table 152. Frame formats

| SB | 7-bit data | PB | STB |
| SB | 8-bit data PB | STB |
RM0402 Rev 6
RXNE RXNE RXNE
Normal mode
Non-matching address
(1)
USART frame
| SB | 8 bit data | STB |
| SB | 9-bit data | STB |
Mute mode
MSv31155V1
Table 152.
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