Quadspi Pins; Table 71. Quadspi Pins; Figure 52. Quadspi Block Diagram When Dual-Flash Mode Is Enabled - ST STM32F412 Reference Manual

RM0402
AHB
12.3.2

QUADSPI pins

Table 71
for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode.
Signal name
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK2_IO0/SO
BK2_IO1/SI
BK2_IO2
BK2_IO3
BK1_nCS
BK2_nCS

Figure 52. QUADSPI block diagram when dual-flash mode is enabled

QUADSPI
Registers /
control
FIFO
lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11
Signal type
Digital output
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Digital input/output
Digital output
Digital output
Clock
management
CLK
BK1_IO0/SO
BK1_IO1/SI
BK1_IO2
BK1_IO3
BK1_nCS
Shift register
BK2_IO0/SO
BK2_IO1/SI
BK2_IO2
BK2_IO3
BK2_nCS

Table 71. QUADSPI pins

Clock to FLASH 1 and FLASH 2
Bidirectional IO in dual/quad modes or serial output
in single mode, for FLASH 1
Bidirectional IO in dual/quad modes or serial input
in single mode, for FLASH 1
Bidirectional IO in quad mode, for FLASH 1
Bidirectional IO in quad mode, for FLASH 1
Bidirectional IO in dual/quad modes or serial output
in single mode, for FLASH 2
Bidirectional IO in dual/quad modes or serial input
in single mode, for FLASH 2
Bidirectional IO in quad mode, for FLASH 2
Bidirectional IO in quad mode, for FLASH 2
Chip select (active low) for FLASH 1. Can also be
used for FLASH 2 if QUADSPI is always used in
dual-flash mode.
Chip select (active low) for FLASH 2. Can also be
used for FLASH 1 if QUADSPI is always used in
dual-flash mode.
RM0402 Rev 6
Quad-SPI interface (QUADSPI)
SPI FLASH 1
CLK
Q0/SI
Q1/SO
Q2/WP
Q3/HOLD
CS
SPI FLASH 2
CLK
Q0/SI
Q1/SO
Q2/WP
Q3/HOLD
CS
Description
MS35316V1
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