Otg Power And Clock Gating Control Register (Otg_Pcgcctl) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

USB on-the-go full-speed (OTG_FS)

Bits 30:29 RXDPID[1:0]: Received data PID

STUPCNT[1:0]: SETUP packet count

Bits 28:19 PKTCNT[9:0]: Packet count

Bits 18:0 XFRSIZ[18:0]: Transfer size

29.15.54 OTG power and clock gating control register (OTG_PCGCCTL)

Address offset: 0xE00

Reset value: 0x200B 8000

This register is available in host and device modes.

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 SUSP: Deep Sleep

Bit 6 PHYSLEEP: PHY in Sleep

Applies to isochronous OUT endpoints only.

This is the data PID received in the last packet for this endpoint.

Applies to control OUT endpoints only.

This field specifies the number of back-to-back SETUP data packets the endpoint can

01: 1 packet

10: 2 packets

11: 3 packets

Indicates the total number of USB packets that constitute the transfer size amount of data for

this endpoint.

This field is decremented every time a packet (maximum size or short packet) is written to

the Rx FIFO.

This field contains the transfer size in bytes for the current endpoint. The core only interrupts

the application after it has exhausted the transfer size amount of data. The transfer size can

be set to the maximum packet size of the endpoint, to be interrupted at the end of each

The core decrements this field every time a packet is read from the Rx FIFO and written to

the external memory.

This bit indicates that the PHY is in Deep Sleep when in L1 state.

This bit indicates that the PHY is in the Sleep state.

RM0402 Rev 6

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