Figure 344. Receive Fifo Read Task - ST STM32F412 Reference Manual

RM0402
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Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in
Figure
SETUP transaction operates in the same way but has only one packet. The
assumptions are:
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–
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Normal bulk and control OUT/SETUP operations
The sequence of operations in (channel 1) is as follows:
1. Initialize channel 1
2. Write the first packet for channel 1
3. Along with the last word write, the core writes an entry to the non-periodic request
queue
4. As soon as the non-periodic queue becomes non-empty, the core attempts to send an
OUT token in the current frame
5. Write the second (last) packet for channel 1
6. The core generates the XFRC interrupt as soon as the last transaction is completed
successfully
7. In response to the XFRC interrupt, de-allocate the channel for other transfers
8. Handling non-ACK responses

Figure 344. Receive FIFO read task

345. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control
The application is attempting to send two maximum-packet-size packets (transfer
size = 1, 024 bytes).
The non-periodic transmit FIFO can hold two packets (128 bytes for FS).
The non-periodic request queue depth = 4.
USB on-the-go full-speed (OTG_FS)
RM0402 Rev 6 1075/1163
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