Dfsdm Filter X Analog Watchdog Low Threshold Register; (Dfsdm_Fltxawltr) - ST STM32F412 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
Bits 31:8 AWHT[23:0]: Analog watchdog high threshold
These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the
16-bit threshold as compared with the analog watchdog filter output (because data coming from
the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event
14.8.10

DFSDM filter x analog watchdog low threshold register

(DFSDM_FLTxAWLTR)

Address offset: 0x124 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:8 AWLT[23:0]: Analog watchdog low threshold
These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event
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28 27 26 25
rw rw rw rw
12 11 10 9
AWLT[7:0]
rw rw rw rw
24 23 22
AWLT[23:8]
rw rw rw
8 7 6
Res. Res.
rw
RM0402 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
Res. Res. BKAWL[3:0]
rw rw
RM0402
17 16
rw rw
1 0
rw rw