ST STM32F412 Reference Manual page 671

RM0402
Slave transmitter
A transmit interrupt status (TXIS) is generated when the FMPI2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit is set in the FMPI2C_CR1 register.
The TXIS bit is cleared when the FMPI2C_TXDR register is written with the next data byte
to be transmitted.
When a NACK is received, the NACKF bit is set in the FMPI2C_ISR register and an
interrupt is generated if the NACKIE bit is set in the FMPI2C_CR1 register. The slave
automatically releases the SCL and SDA lines in order to let the master perform a STOP or
a RESTART condition. The TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the FMPI2C_CR1 register, the
STOPF flag is set in the FMPI2C_ISR register and an interrupt is generated. In most
applications, the SBC bit is usually programmed to '0'. In this case, If TXE = 0 when the
slave address is received (ADDR=1), the user can choose either to send the content of the
FMPI2C_TXDR register as the first data byte, or to flush the FMPI2C_TXDR register by
setting the TXE bit in order to program a new data byte.
In Slave byte control mode (SBC=1), the number of bytes to be transmitted must be
programmed in NBYTES in the address match interrupt subroutine (ADDR=1). In this case,
the number of TXIS events during the transfer corresponds to the value programmed in
NBYTES.
Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the FMPI2C_TXDR register content in the ADDR subroutine, in order to
program the first data byte. The first data byte to be sent must be previously programmed in
the FMPI2C_TXDR register:
•
This data can be the data written in the last TXIS event of the previous transmission
message.
•
If this data byte is not the one to be sent, the FMPI2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error is
generated (the OVR flag is set).
If a TXIS event is needed, (transmit interrupt or transmit DMA request), the user must
set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
RM0402 Rev 6 671/1163
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