Figure 222. Master Initialization Flowchart; Figure 223. 10-Bit Address Read Access With Head10R=0 - ST STM32F412 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
master re-launches automatically the slave address transmission until ACK is received. In
this case ADDRCF must be set if a NACK is received from the slave, in order to stop
sending the slave address.
If the FMPI2C is addressed as a slave (ADDR=1) while the START bit is set, the FMPI2C
switches to slave mode and the START bit is cleared, when the ADDRCF bit is set.
Note: The same procedure is applied for a Repeated Start condition. In this case BUSY=1.
Initialization of a master receiver addressing a 10-bit address slave
•
If the slave address is in 10-bit format, the user can choose to send the complete read
sequence by clearing the HEAD10R bit in the FMPI2C_CR2 register. In this case the
master automatically sends the following complete sequence after the START bit is set:
(Re)Start + Slave address 10-bit header Write + Slave address 2nd byte + REStart +
Slave address 10-bit header Read
1 1 1 1 0 X X
Slave address
S
1st 7 bits
680/1163

Figure 222. Master initialization flowchart

Enable interrupts and/or DMA in FMPI2C_CR1

Figure 223. 10-bit address read access with HEAD10R=0

0
Slave address
R/W A1
2nd byte
Write
RM0402 Rev 6
Master
initialization
Initial settings
End
1 1 1 1 0 X X 1
Slave address
A2 Sr R/W
1st 7 bits
Read
RM0402
MSv35968V1
A3 DATA A DATA
MSv41066V1
A P