Table 61. Fsmc_Bcrx Bitfields (Mode D); Table 62. Fsmc_Btrx Bitfields (Mode D) - ST STM32F412 Reference Manual

RM0402
The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit number
31:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0

Table 61. FSMC_BCRx bitfields (mode D)

Bit name
Reserved 0x000
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Set according to memory support
MWID As needed
MTYP As needed
MUXEN 0x0
MBKEN 0x1

Table 62. FSMC_BTRx bitfields (mode D)

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 1.
RM0402 Rev 6
Flexible static memory controller (FSMC)
Value to set
Value to set
267/1163
287