Table 54. Fsmc_Bwtrx Bitfields (Mode A); Figure 37. Mode 2 And Mode B Read Access Waveforms - ST STM32F412 Reference Manual

Flexible static memory controller (FSMC)
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Mode 2/B - NOR Flash
260/1163

Table 54. FSMC_BWTRx bitfields (mode A)

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for write
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET
Minimum value for ADDSET is 0.

Figure 37. Mode 2 and mode B read access waveforms

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
Value to set
Memory transaction
ADDSET
HCLK cycles
RM0402 Rev 6
data driven
by memory
DATAST
HCLK cycles
RM0402
MS34481V2