Spi Rx Crc Register (Spi_Rxcrcr) (Not Used In I 2 S Mode); Spi Tx Crc Register (Spi_Txcrcr) (Not Used In I 2 S Mode) - ST STM32F412 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I
Address offset: 0x14
Reset value: 0x0000
15 14 13
r r r
Bits 15:0 RXCRC[15:0]: Rx CRC register
When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in
the SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF
bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected
(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY Flag is set could return an incorrect value.These
26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I
Address offset: 0x18
Reset value: 0x0000
15 14 13
r r r
Bits 15:0 TXCRC[15:0]: Tx CRC register
Note: A read to this register when the BSY flag is set could return an incorrect value. These
858/1163
12 11 10 9
r r r r
bits are not used for I
12 11 10 9
r r r r
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF
bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected
(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16
standard.
bits are not used for I
8 7 6
RXCRC[15:0]
r r r
2
S mode.
8 7 6
TXCRC[15:0]
r r r
2
S mode.
RM0402 Rev 6
2
S mode)
5 4 3 2
r r r r
2
S mode)
5 4 3 2
r r r r
RM0402
1 0
r r
1 0
r r