Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4); Tim1&Tim8 Break And Dead-Time Register (Timx_Bdtr) - ST STM32F412 Reference Manual

Advanced-control timers (TIM1&TIM8)
16.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR4[15:0]: Capture/Compare value
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
16.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR)
Address offset: 0x44
Reset value: 0x0000
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIMx_BDTR register.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register).
See OC/OCN enable description for more details
capture/compare enable register (TIMx_CCER) on page
Bit 14 AOE: Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break input is
not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
478/1163
12 11 10 9
rw rw rw rw
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
in TIMx_BDTR register).
8 7 6
CCR4[15:0]
rw rw rw
8 7 6
rw rw rw
(Section 16.4.9: TIM1&TIM8
RM0402 Rev 6
5 4 3 2
rw rw rw rw
5 4 3 2
DTG[7:0]
rw rw rw rw
471).
RM0402
1 0
rw rw
1 0
rw rw