Dfsdm Pins And Internal Signals; Table 84. Dfsdm External Pins; Table 85. Dfsdm Internal Signals; Table 86. Dfsdm Triggers Connection - ST STM32F412 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
1. This example shows 2 DFSDM filters and 4 input channels.
14.4.2

DFSDM pins and internal signals

Name
VDD
VSS
CKIN[3:0]
DATIN[3:0]
CKOUT
EXTRG[1:0]
dfsdm_jtrg[10:0]
dfsdm_break[3:0]
dfsdm_dma[1:0]
dfsdm_it[1:0]
dfsdm_jtrg0
dfsdm_jtrg1
dfsdm_jtrg2
dfsdm_jtrg3
dfsdm_jtrg4
dfsdm_jtrg5
dfsdm_jtrg6
dfsdm_jtrg7
dfsdm_jtrg8
dfsdm_jtrg9
dfsdm_jtrg10
352/1163

Table 84. DFSDM external pins

Signal Type
Power supply
Power supply
Clock input
Data input
Clock output
External trigger
signal

Table 85. DFSDM internal signals

Name Signal Type
Internal/
external trigger
signal
break signal
output
DMA request
signal
Interrupt
request signal

Table 86. DFSDM triggers connection

Trigger name
Digital power supply.
Digital ground power supply.
Clock signal provided from external Σ∆ modulator. FT input.
Data signal provided from external Σ∆ modulator. FT input.
Clock output to provide clock signal into external Σ∆
modulator.
Input trigger from two EXTI signals to start analog
conversion (from GPIOs: EXTI11, EXTI15).
Input trigger from internal/external trigger sources to start
analog conversion, see
Break signals event generation from Analog watchdog or
short-circuit detector
DMA request signal from each DFSDM_FLTx (x=0..1):
end of injected conversion event.
Interrupt signal for each DFSDM_FLTx (x=0..1)
RM0402 Rev 6
Remarks
Remarks
Table 86 for details.
Trigger source
TIM1_TRGO
TIM3_TRGO
TIM8_TRGO
TIM10_OC1
N/A
TIM4_TRGO
N/A
TIM6_TRGO
N/A
EXTI11
EXTI15
RM0402