Continuous And Fast Continuous Modes; Request Precedence - ST STM32F412 Reference Manual

RM0402
already been issued but not yet completed. A regular conversion can be pending if it was
interrupted by an injected conversion or if it was started while an injected conversion was in
progress. This pending regular conversion is then delayed and is performed when all
injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit
in DFSDM_FLTxRDATAR register.
14.4.16

Continuous and fast continuous modes

Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in
continuous mode. RCONT=1 means that the channel selected by RCH[1:0] is converted
repeatedly after '1' is written to RSWSTART.
The regular conversions executing in continuous mode can be stopped by writing '0' to
RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the
DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh
data if converting continuously from one channel because data inside the filter is valid from
previously sampled continuous data. The speed increase depends on the chosen filter
order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by
RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is
finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
if FAST = 1 (except first conversion):
in case F
Continuous mode is not available for injected conversions. Injected conversions can be
started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to
DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is
performed, then regular continuous conversion is restarted from the next conversion cycle
(like new regular continuous conversion is applied for new channel selection - even if there
is no change in DFSDM_FLTxCR1 register).
14.4.17

Request precedence

An injected conversion has a higher precedence than a regular conversion. A regular
conversion which is already in progress is immediately interrupted by the request of an
injected conversion; this regular conversion is restarted after the injected conversion
finishes.
x
for Sinc filters:
t = CNVCNT/f
DFSDMCLK
for FastSinc filter:
t = CNVCNT/f
DFSDMCLK
x
for Sinc and FastSinc filters:
t = CNVCNT/f
DFSDMCLK
= FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
OSR
t = I / f (... but CNVCNT=0)
OSR CKIN
Digital filter for sigma delta modulators (DFSDM)
= [F * (I
OSR OSR
= [F * (I
OSR OSR
= [F * I ] / f
OSR OSR
RM0402 Rev 6
-1 + F ) + F ] / f
ORD ORD
-1 + 4) + 2] / f
CKIN
CKIN
CKIN
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