ST STM32F412VE Manuals
Manuals and User Guides for ST STM32F412VE. We have 1 ST STM32F412VE manual available for free PDF download: Reference Manual
ST STM32F412VE Reference Manual (1163 pages)
advanced Arm-based 32-bit MCUs
Brand: ST
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Category: Microcontrollers
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Size: 18 MB
Table of Contents
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Glossary46
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I-Bus48
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D-Bus48
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S-Bus48
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Busmatrix48
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Introduction49
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Bit Banding54
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Introduction58
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Erase64
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Programming65
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Interrupts66
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Option Bytes66
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Sleep Mode95
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Stop Mode97
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Standby Mode100
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PWR Register Map108
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Reset109
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System Reset109
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Power Reset110
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Clocks111
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HSE Clock113
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HSI Clock114
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LSE Clock115
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LSI Clock116
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RTC/AWU Clock117
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Watchdog Clock117
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RCC Registers121
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RCC Register Map164
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Port Pins177
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GPIO Registers179
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(X = a179
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(X = a180
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(X = a182
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(X = a184
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SYSCFG Registers187
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(Syscfg_Exticr1)189
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(Syscfg_Exticr2)189
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(Syscfg_Exticr3)190
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(Syscfg_Exticr4)191
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DMA Introduction195
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DMA Overview197
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DMA Transactions198
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Arbiter200
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DMA Streams200
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Circular Mode205
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Fifo208
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Flow Controller213
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Error Management215
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DMA Interrupts216
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DMA Registers217
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DMA Register Map227
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NVIC Features231
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EXTI Registers239
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Introduction246
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AHB Interface248
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And Transactions254
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Introduction288
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QUADSPI Pins289
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QUADSPI Usage298
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Ncs Behavior301
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ADC Introduction317
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ADC Clock319
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Timing Diagram321
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Analog Watchdog321
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Scan Mode322
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Data Alignment325
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Data Management329
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Using the DMA329
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ADC Interrupts332
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ADC Registers333
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ADC Register Map346
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Introduction348
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Integrator Unit367
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Analog Watchdog367
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Extreme Detector370
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Data Unit Block371
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DFSDM Interrupts374
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(Dfsdm_Fltxawsr)393
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Introduction401
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RNG Operation405
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RNG Clocking406
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Error Management406
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RNG Interrupts407
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Introduction408
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Data Collection408
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RNG Registers409
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RNG Register Map412
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Time-Base Unit415
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Counter Modes417
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Clock Selection428
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PWM Input Mode435
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PWM Mode437
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One-Pulse Mode447
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Debug Mode456
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Time-Base Unit485
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Counter Modes487
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Clock Selection496
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PWM Input Mode502
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PWM Mode505
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One-Pulse Mode508
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Debug Mode521
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Time-Base Unit548
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Counter Modes550
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Clock Selection553
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PWM Mode560
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One-Pulse Mode561
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Debug Mode566
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(Timx_Ccmr1)584
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(Timx_Ccer)587
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Introduction592
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Time-Base Unit593
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Counting Mode595
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Clock Source598
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Debug Mode599
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TIM6/7 Registers600
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Debug Mode606
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IWDG Registers607
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Debug Mode614
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WWDG Registers615
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Introduction618
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Tamper Detection630
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Alarm Output632
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RTC Interrupts633
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RTC Registers634
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(Rtc_Tafcr)649
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RTC Register Map653
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Introduction656
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Mode Selection660
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Software Reset665
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Data Transfer666
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Smbus Slave Mode695
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Error Conditions702
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DMA Requests704
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Debug Mode705
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FMPI2C Registers707
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C Introduction723
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Mode Selection725
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I2C Slave Mode726
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I2C Master Mode729
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Error Conditions735
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Smbus737
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DMA Requests740
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I 2 C Interrupts742
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I 2 C Debug Mode744
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I 2 C Registers744
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I2C Register Map757
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Transmitter764
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Receiver767
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Parity Control785
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Smartcard791
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USART Interrupts799
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USART Registers800
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Introduction811
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I2S Features813
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SPI Status Flags829
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SPI Error Flags830
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TI Mode831
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CRC Calculation832
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SPI Interrupts834
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Figure 283. I835
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I2S Full-Duplex836
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Figure 289. I839
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Clock Generator843
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Figure 303. I844
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I 2 S Slave Mode848
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I 2 S Interrupts851
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DMA Features851
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Table 158. I851
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Mode857
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SPI Register Map862
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SDIO Adapter867
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Card Reset880
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Block Write881
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Block Read882
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SD I/O Mode895
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Response Formats899
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R1B900
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R4 (Fast I/O)901
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R4B901
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SDIO Interrupts904
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HW Flow Control904
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SDIO Registers905
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SDIO Response 1908
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Introduction922
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Tx Mailboxes923
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Normal Mode925
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Test Mode927
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Silent Mode927
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Loop Back Mode927
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Message Storage936
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Error Management938
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Bit Timing938
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Bxcan Interrupts941
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CAN Registers942
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Introduction967
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General Features968
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OTG_FS Core972
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OTG Detections973
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SRP-Capable Host979
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USB Host States979
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Host Channels981
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Host Scheduler982
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Host Sofs983
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Peripheral Sofs983
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CSR Memory Map992
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OTG_FS Registers996
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(Otg_Dieptxf0)1017
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(Otg_Hnptxsts)1018
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(Otg_Hptxfsiz)1025
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(Otg_Dieptxfx)1025
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(Otg_Hfnum)1028
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(Otg_Hptxsts)1028
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(Otg_Haintmsk)1030
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(Otg_Diepmsk)1042
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(Otg_Doepmsk)1043
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(Otg_Daintmsk)1045
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OTG Device1045
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(Otg_Dvbusdis)1045
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OTG Device1046
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(Otg_Dvbuspulse)1046
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(Otg_Diepempmsk)1046
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(Otg_Diepctl0)1047
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(Otg_Dieptsiz0)1052
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(Otg_Dtxfstsx)1053
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(Otg_Doepctl0)1055
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(Otg_Doeptsiz0)1058
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(Otg_Doepctlx)1059
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(Otg_Doeptsizx)1061
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Core Initialization1071
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Host Initialization1072
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Debug Support (DBG)1123
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Overview1123
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SWJ Debug Port Pins1126
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JTAG TAP Connection1128
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MCU Device ID Code1130
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Boundary Scan TAP1130
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Cortex1131
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JTAG Debug Port1131
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SW Debug Port1133
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SW Protocol Sequence1133
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SW-DP Registers1135
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SW-AP Registers1136
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Core Debug1137
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General Description1139
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General Description1141
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Main ETM Registers1141
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11431143
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Introduction1146
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TRACE Pin Assignment1148
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TPUI Formatter1149
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Synchronous Mode1150
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Asynchronous Mode1151
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TPIU Registers1151
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DBG Register Map1153
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Flash Size1155
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Revision History1157
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