Clock Selection; Figure 145. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F412 Reference Manual

General-purpose timers (TIM2 to TIM5)
17.3.3

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin (TIx)
•
External clock mode2: external trigger input (ETR) available on TIM2, TIM3 and TIM4
only.
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, Timer can be configured to act as a prescaler for Timer 2. Refer to
timer as prescaler for another
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 145
without prescaler.

Figure 145. Control circuit in normal mode, internal clock divided by 1

Counter clock = CK_CNT = CK_PSC
External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
496/1163
shows the behavior of the control circuit and the upcounter in normal mode,
Internal clock
CEN=CNT_EN
UG
CNT_INIT
Counter register
RM0402 Rev 6
for more details.
3 2 33 34 35 36
31
00 01 02 06
03 04 05
RM0402
Using one
07
MS31085V2