RM0402
14.4
DFSDM functional description
14.4.1
DFSDM block diagram
Parallel input data
register 0
EXTRG[1:0]
CKOUT
DATIN0
CKIN0
DATIN3
CKIN3
Control unit
Configuration
registers
DMA, interrupt, break
control, clock control
Figure 67. Single DFSDM block diagram
APB bus
Sample 1
Sample 0
Sample 1
Sample 0
Parallel input data
register 3
Clock
Mode
control
control
Serial transceiver 0
Clock
Mode
control
control
Serial transceiver 3
Interrupt,
break
1's, 0's counter
threshold
Short circuit
detector 0
1's, 0's counter
threshold
Short circuit
detector 3
Digital filter for sigma delta modulators (DFSDM)
16
16
Data 0
Clock 0
16
Data 1
Clock 1
Data in
16
Clock in
4 watchdog filters
4 watchdog comparators
High threshold
Filter 0
Low threshold
config
Analog watchdog 0
High threshold
Filter 1
Low threshold
config
Analog watchdog 1
Interrupts and events:
1) end of conversion
2) analog watchdog
Extremes
3) short circuit detection
detector 0
4) overrun
RM0402 Rev 6
Filter
Oversampling
Oversampling
order
ratio
x
Sinc
filter 0
Integrator unit 0
Filter
Oversampling
Oversampling
order
ratio
x
Sinc
filter 1
Integrator unit 1
Right bit-shift
count
Calibration data
correction unit
DFSDM data 0
Interrupt,
break
Data output
Interrupt,
break
Maximum value
Maximum value
Minimum value
Minimum value
Extremes
detector 1
ratio
ratio
Right bit-shift
count
Calibration data
correction unit
DFSDM data 1
APB bus
MSv40119V4
351/1163
400
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