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RM0402
Bit 2 JEOC1: Injected channel end of conversion of ADC1
Bit 1 EOC1: End of conversion of ADC1
Bit 0 AWD1: Analog watchdog flag of ADC1
13.12.16 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and V
Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT
Bit 22 VBATE: V
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 ADCPRE: ADC prescaler
Note: 00: PCLK2 divided by 2
Bits 15:0 Reserved, must be kept at reset value.
This bit is a copy of the JEOC bit in the ADC1_SR register.
This bit is a copy of the EOC bit in the ADC1_SR register.
This bit is a copy of the AWD bit in the ADC1_SR register.
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is set and cleared by software to enable/disable the temperature sensor and the
V
channel.
REFINT
0: Temperature sensor and V
1: Temperature sensor and V
conversion is performed.
enable
BAT
This bit is set and cleared by software to enable/disable the V
0: V
channel disabled
BAT
1: V
channel enabled
BAT
Set and cleared by software to select the frequency of the clock to the ADC. The clock is
common for all the ADCs.
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
24
23
22
Res.
TSVREFE VBATE
Res.
rw
rw
8
7
6
Res.
Res.
Res.
Res.
enable
REFINT
channel disabled
REFINT
channel enabled
REFINT
RM0402 Rev 6
Analog-to-digital converter (ADC)
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
channel.
BAT
17
16
ADCPRE
rw
rw
1
0
Res.
Res.
345/1163
347
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