ST STM32F412 Reference Manual page 383

RM0402
Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion
0: The DMA channel is not enabled to read regular data
1: The DMA channel is enabled to read regular data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 20 Reserved, must be kept at reset value.
Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM_FLT0
0: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion
is launched in DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 18 RCONT: Continuous mode selection for regular conversions
0: The regular channel is converted just once for each conversion request
1: The regular channel is converted repeatedly after each conversion request
Writing '0' to this bit while a continuous regular conversion is already in progress stops the
continuous mode immediately.
Bit 17 RSWSTART: Software start of a conversion on the regular channel
0: Writing '0' has no effect
1: Writing '1' makes a request to start a conversion on the regular channel and causes RCIP to
become '1'. If RCIP=1 already, writing to RSWSTART has no effect. Writing '1' has no effect if
RSYNC=1.
This bit is always read as '0'.
Bits 16:15 Reserved, must be kept at reset value.
Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions
00: Trigger detection is disabled
01: Each rising edge on the selected trigger makes a request to launch an injected conversion
10: Each falling edge on the selected trigger makes a request to launch an injected conversion
11: Both rising edges and falling edges on the selected trigger make requests to launch injected
conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bits 12:11 Reserved, must be kept at reset value.
Bits 10:8 JEXTSEL[2:0]: Trigger signal selection for launching injected conversions
0x0-0x7: Trigger inputs selected by the following table.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Refer to
Bits 7:6 Reserved, must be kept at reset value.
DFSDM_FLT0 DFSDM_FLT1
dfsdm_jtrg0 dfsdm_jtrg0
dfsdm_jtrg1 dfsdm_jtrg1
dfsdm_jtrg2 dfsdm_jtrg2
dfsdm_jtrg3 dfsdm_jtrg3
dfsdm_jtrg5 dfsdm_jtrg5
dfsdm_jtrg7 dfsdm_jtrg7
dfsdm_jtrg9 dfsdm_jtrg9
dfsdm_jtrg10 dfsdm_jtrg10
Table 86: DFSDM triggers
Digital filter for sigma delta modulators (DFSDM)
connection.
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