Quadspi Register Map; Table 73. Quadspi Register Map And Reset Values - ST STM32F412 Reference Manual

Quad-SPI interface (QUADSPI)
12.5.14

QUADSPI register map

Register
Offset
name
QUADSPI_CR
0x0000
Reset value
QUADSPI_DCR
0x0004
Reset value
QUADSPI_SR
0x0008
Reset value
QUADSPI_FCR
0x000C
Reset value
QUADSPI_DLR
0x0010
Reset value
QUADSPI_CCR
0x0014
Reset value
QUADSPI_AR
0x0018
Reset value
QUADSPI_ABR
0x001C
Reset value
QUADSPI_DR
0x0020
Reset value
QUADSPI_
PSMKR
0x0024
Reset value
QUADSPI_
PSMAR
0x0028
Reset value
QUADSPI_PIR
0x002C
Reset value
QUADSPI_
LPTR
0x0030
Reset value
Refer to
316/1163

Table 73. QUADSPI register map and reset values

PRESCALER[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Section 2.2 on page 49
0 0 0 0 0 0
FSIZE[4:0]
0 0 0 0 0
DL[31:0]
0 0 0 0 0 0 0 0 0
DCYC[4:0]
0 0 0 0 0 0 0 0 0
ADDRESS[31:0]
0 0 0 0 0 0 0 0 0
ALTERNATE[31:0]
0 0 0 0 0 0 0 0 0
DATA[31:0]
0 0 0 0 0 0 0 0 0
MASK[31:0]
0 0 0 0 0 0 0 0 0
MATCH[31:0]
0 0 0 0 0 0 0 0 0
0 0
0 0
for the register boundary addresses.
RM0402 Rev 6
FTHRES
[4:0]
0 0 0 0 0 0 0
CSHT
0 0 0
FLEVEL[5:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
INSTRUCTION[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
INTERVAL[15:0]
0 0 0 0 0 0 0 0 0
TIMEOUT[15:0]
0 0 0 0 0 0 0 0 0
RM0402
0 0 0 0 0
0
0 0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0