Otg Host Channel X Interrupt Register (Otg_Hcintx) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

USB on-the-go full-speed (OTG_FS)

Bits 21:20 MCNT[1:0]: Multicount

Note: This field must be set to at least 01.

Bits 19:18 EPTYP[1:0]: Endpoint type

Bit 17 LSDEV: Low-speed device

Bit 16 Reserved, must be kept at reset value.

Bit 15 EPDIR: Endpoint direction

Bits 14:11 EPNUM[3:0]: Endpoint number

Bits 10:0 MPSIZ[10:0]: Maximum packet size

29.15.29 OTG host channel x interrupt register (OTG_HCINTx)

Address offset: 0x508 + 0x20 * x, (x = 0 to 11)

Reset value: 0x0000 0000

This register indicates the status of a channel with respect to USB- and AHB-related events.

It is shown in

interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the

application can read this register, it must first read the host all channels interrupt

(OTG_HAINT) register to get the exact channel number for the host channel-x interrupt

corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

This field indicates to the host the number of transactions that must be executed per frame

for this periodic endpoint. For non-periodic transfers, this field is not used

00: Reserved. This field yields undefined results

01: 1 transaction

10: 2 transactions per frame to be issued for this endpoint

11: 3 transactions per frame to be issued for this endpoint

Indicates the transfer type selected.

01: Isochronous

11: Interrupt

This field is set by the application to indicate that this channel is communicating to a low-

speed device.

Indicates whether the transaction is IN or OUT.

Indicates the endpoint number on the device serving as the data source or sink.

Indicates the maximum packet size of the associated endpoint.

342. The application must read this register when the host channels

RM0402 Rev 6

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