Calibration Clock Output - ST STM32F412 Reference Manual

RM0402
Edge detection on tamper inputs
If the TAMPFLT bits are "00", the TAMPER pins generate tamper detection events
(RTC_TAMP[2:1]) when either a rising edge is observed or an falling edge is observed
depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the
TAMPER inputs are deactivated when edge detection is selected.
Caution: To avoid losing tamper detection events, the signal used for edge detection is logically
ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the
TAMPERx pin is enabled.
•
When TAMPxTRG = 0: if the TAMPERx alternate function is already high before
tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon
as TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE
was set.
• When TAMPxTRG = 1: if the TAMPERx alternate function is already low before tamper
detection is enabled, a tamper event is detected as soon as TAMPERx is enabled
(even if there was no falling edge on TAMPERx after TAMPxE was set.
After a tamper event has been detected and cleared, the TAMPERx alternate function
should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the
backup registers (RTC_BKPxR). This prevents the application from writing to the backup
registers while the TAMPERx value still indicates a tamper detection. This is equivalent to a
level detection on the TAMPERx alternate function.
Note: Tamper detection is still active when V
of the backup registers, the pin to which the TAMPER alternate function is mapped should
be externally tied to the correct level.
Level detection with filtering on tamper inputs
Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits
(TAMP1TRG/TAMP2TRG).
The TAMPER inputs are pre-charged through the I/O internal pull-up resistance before its
state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the precharge
is determined by the TAMPPRCH bits, allowing for larger capacitances on the tamper
inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.
TAMPER alternate function detection
The TAMPER1 additional function is mapped to RTC_AF1 pin.
22.3.14

Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output. If the COSEL bit in the RTC_CR register is reset and
PREDIV_A = 0x7F, the RTC_CALIB frequency is f
calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz.
power is switched off. To avoid unwanted resetting
DD
RTCCLK
RM0402 Rev 6
Real-time clock (RTC)
. This corresponds to a
/64
631/1163
655