ST STM32F412ZET7 Manuals
Manuals and User Guides for ST STM32F412ZET7. We have 1 ST STM32F412ZET7 manual available for free PDF download: Reference Manual
ST STM32F412ZET7 Reference Manual (1163 pages)
advanced Arm-based 32-bit MCUs
Brand: ST
|
Category: Microcontrollers
|
Size: 18 MB
Table of Contents
-
Glossary46
-
I-Bus48
-
D-Bus48
-
S-Bus48
-
Busmatrix48
-
Introduction49
-
Bit Banding54
-
Introduction58
-
Erase64
-
Programming65
-
Interrupts66
-
Option Bytes66
-
Sleep Mode95
-
Stop Mode97
-
Standby Mode100
-
PWR Register Map108
-
Reset109
-
System Reset109
-
Power Reset110
-
Clocks111
-
HSE Clock113
-
HSI Clock114
-
LSE Clock115
-
LSI Clock116
-
RTC/AWU Clock117
-
Watchdog Clock117
-
RCC Registers121
-
RCC Register Map164
-
Port Pins177
-
GPIO Registers179
-
(X = a179
-
(X = a180
-
(X = a182
-
(X = a184
-
SYSCFG Registers187
-
(Syscfg_Exticr1)189
-
(Syscfg_Exticr2)189
-
(Syscfg_Exticr3)190
-
(Syscfg_Exticr4)191
-
DMA Introduction195
-
DMA Overview197
-
DMA Transactions198
-
Arbiter200
-
DMA Streams200
-
Circular Mode205
-
Fifo208
-
Flow Controller213
-
Error Management215
-
DMA Interrupts216
-
DMA Registers217
-
DMA Register Map227
-
NVIC Features231
-
EXTI Registers239
-
Introduction246
-
AHB Interface248
-
And Transactions254
-
Introduction288
-
QUADSPI Pins289
-
QUADSPI Usage298
-
Ncs Behavior301
-
ADC Introduction317
-
ADC Clock319
-
Timing Diagram321
-
Analog Watchdog321
-
Scan Mode322
-
Data Alignment325
-
Data Management329
-
Using the DMA329
-
ADC Interrupts332
-
ADC Registers333
-
ADC Register Map346
-
Introduction348
-
Integrator Unit367
-
Analog Watchdog367
-
Extreme Detector370
-
Data Unit Block371
-
DFSDM Interrupts374
-
(Dfsdm_Fltxawsr)393
-
Introduction401
-
RNG Operation405
-
RNG Clocking406
-
Error Management406
-
RNG Interrupts407
-
Introduction408
-
Data Collection408
-
RNG Registers409
-
RNG Register Map412
-
Time-Base Unit415
-
Counter Modes417
-
Clock Selection428
-
PWM Input Mode435
-
PWM Mode437
-
One-Pulse Mode447
-
Debug Mode456
-
Time-Base Unit485
-
Counter Modes487
-
Clock Selection496
-
PWM Input Mode502
-
PWM Mode505
-
One-Pulse Mode508
-
Debug Mode521
-
Time-Base Unit548
-
Counter Modes550
-
Clock Selection553
-
PWM Mode560
-
One-Pulse Mode561
-
Debug Mode566
-
(Timx_Ccmr1)584
-
(Timx_Ccer)587
-
Introduction592
-
Time-Base Unit593
-
Counting Mode595
-
Clock Source598
-
Debug Mode599
-
TIM6/7 Registers600
-
Debug Mode606
-
IWDG Registers607
-
Debug Mode614
-
WWDG Registers615
-
Introduction618
-
Tamper Detection630
-
Alarm Output632
-
RTC Interrupts633
-
RTC Registers634
-
(Rtc_Tafcr)649
-
RTC Register Map653
-
Introduction656
-
Mode Selection660
-
Software Reset665
-
Data Transfer666
-
Smbus Slave Mode695
-
Error Conditions702
-
DMA Requests704
-
Debug Mode705
-
FMPI2C Registers707
-
C Introduction723
-
Mode Selection725
-
I2C Slave Mode726
-
I2C Master Mode729
-
Error Conditions735
-
Smbus737
-
DMA Requests740
-
I 2 C Interrupts742
-
I 2 C Debug Mode744
-
I 2 C Registers744
-
I2C Register Map757
-
Transmitter764
-
Receiver767
-
Parity Control785
-
Smartcard791
-
USART Interrupts799
-
USART Registers800
-
Introduction811
-
I2S Features813
-
SPI Status Flags829
-
SPI Error Flags830
-
TI Mode831
-
CRC Calculation832
-
SPI Interrupts834
-
Figure 283. I835
-
I2S Full-Duplex836
-
Figure 289. I839
-
Clock Generator843
-
Figure 303. I844
-
I 2 S Slave Mode848
-
I 2 S Interrupts851
-
DMA Features851
-
Table 158. I851
-
Mode857
-
SPI Register Map862
-
SDIO Adapter867
-
Card Reset880
-
Block Write881
-
Block Read882
-
SD I/O Mode895
-
Response Formats899
-
R1B900
-
R4 (Fast I/O)901
-
R4B901
-
SDIO Interrupts904
-
HW Flow Control904
-
SDIO Registers905
-
SDIO Response 1908
-
Introduction922
-
Tx Mailboxes923
-
Normal Mode925
-
Test Mode927
-
Silent Mode927
-
Loop Back Mode927
-
Message Storage936
-
Error Management938
-
Bit Timing938
-
Bxcan Interrupts941
-
CAN Registers942
-
Introduction967
-
General Features968
-
OTG_FS Core972
-
OTG Detections973
-
SRP-Capable Host979
-
USB Host States979
-
Host Channels981
-
Host Scheduler982
-
Host Sofs983
-
Peripheral Sofs983
-
CSR Memory Map992
-
OTG_FS Registers996
-
(Otg_Dieptxf0)1017
-
(Otg_Hnptxsts)1018
-
(Otg_Hptxfsiz)1025
-
(Otg_Dieptxfx)1025
-
(Otg_Hfnum)1028
-
(Otg_Hptxsts)1028
-
(Otg_Haintmsk)1030
-
(Otg_Diepmsk)1042
-
(Otg_Doepmsk)1043
-
(Otg_Daintmsk)1045
-
OTG Device1045
-
(Otg_Dvbusdis)1045
-
OTG Device1046
-
(Otg_Dvbuspulse)1046
-
(Otg_Diepempmsk)1046
-
(Otg_Diepctl0)1047
-
(Otg_Dieptsiz0)1052
-
(Otg_Dtxfstsx)1053
-
(Otg_Doepctl0)1055
-
(Otg_Doeptsiz0)1058
-
(Otg_Doepctlx)1059
-
(Otg_Doeptsizx)1061
-
Core Initialization1071
-
Host Initialization1072
-
Debug Support (DBG)1123
-
Overview1123
-
SWJ Debug Port Pins1126
-
JTAG TAP Connection1128
-
MCU Device ID Code1130
-
Boundary Scan TAP1130
-
Cortex1131
-
JTAG Debug Port1131
-
SW Debug Port1133
-
SW Protocol Sequence1133
-
SW-DP Registers1135
-
SW-AP Registers1136
-
Core Debug1137
-
General Description1139
-
General Description1141
-
Main ETM Registers1141
-
11431143
-
Introduction1146
-
TRACE Pin Assignment1148
-
TPUI Formatter1149
-
Synchronous Mode1150
-
Asynchronous Mode1151
-
TPIU Registers1151
-
DBG Register Map1153
-
Flash Size1155
-
Revision History1157
Advertisement
Advertisement