Compensation Cell Control Register (Syscfg_Cmpcr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

System configuration controller (SYSCFG)

Bit 2 PVDL: PVD lock

Bit 1 Reserved, must be kept at reset value.

Bit 0 CLL: core lockup lock

Compensation cell control register (SYSCFG_CMPCR)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 READY: Compensation cell ready flag

Bits 7:2 Reserved, must be kept at reset value.

Bit 0 CMP_PD: Compensation cell power-down

This bit is set by software. It can be cleared only by a system reset. It enables and

locks the PVD connection to TIM1/8 Break input. It also locks (write protection) the

PVDE and PVDS[2:0] bits of PWR_CR register.

0: PVD interrupt not connected to TIM1/8 Break input. PVDE and PVDS[2:0] can be

read and modified

1: PVD interrupt connected to TIM1/8 Break input. PVDE and PVDS[2:0] are read-

This bit is set and cleared by software. It enables and locks the LOCKUP (Hardfault)

output of the Cortex

-M4 with FPU LOCKUP output not connected to TIM1/8 Break input

-M4 with FPU LOCKUP output connected to TIM1/8 Break input

0: I/O compensation cell not ready

1: O compensation cell ready

0: I/O compensation cell power-down mode

1: I/O compensation cell enabled

-M4 with FPU core with TIM1/8 Break input.

RM0402 Rev 6

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