Dfsdm Filter X Analog Watchdog Status Register; (Dfsdm_Fltxawsr); Dfsdm Filter X Analog Watchdog Clear Flag Register; (Dfsdm_Fltxawcfr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

DFSDM filter x analog watchdog status register

Address offset: 0x128 + 0x80 * x, (x = 0 to 1)

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 AWHTF[3:0]: Analog watchdog high threshold flag

AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by

software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.

Bits 7:4 Reserved, must be kept at reset value.

Bits 3:0 AWLTF[3:0]: Analog watchdog low threshold flag

AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by

software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.

All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.

Address offset: 0x12C + 0x80 * x, (x = 0 to 1)

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

CLRAWHTF[3:0]

Digital filter for sigma delta modulators (DFSDM)

RM0402 Rev 6

CLRAWLTF[3:0]

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