Digital filter for sigma delta modulators (DFSDM)
Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate)
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (F
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length)
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
from Sinc filter will be summed into one output data sample from the integrator. The output data rate
from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).
14.8.7
DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR)
Address offset: 0x118 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31
30
29
r
r
r
15
14
13
r
r
r
Bits 31:8 JDATA[23:0]: Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this
field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 JDATACH[1:0]: Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[1:0] is updated to
indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the
channel indicated by JDATACH[1:0].
Note:
DMA may be used to read the data from this register. Half-word accesses may be used to
read only the MSBs of conversion data.
Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not
read this register if DMA is activated to read data from this register.
390/1163
28
27
26
25
r
r
r
r
12
11
10
9
JDATA[7:0]
r
r
r
r
24
23
22
JDATA[23:8]
r
r
r
8
7
6
Res.
Res.
r
RM0402 Rev 6
= FOSR[9:0] +1). This
OSR
21
20
19
18
r
r
r
r
5
4
3
2
Res.
Res.
Res.
Res.
RM0402
17
16
r
r
1
0
JDATACH[1:0]
r
r
Need help?
Do you have a question about the STM32F412 and is the answer not in the manual?