ST STM32F412 Reference Manual page 731

RM0402
The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
•
In 7-bit addressing mode,
–
–
•
In 10-bit addressing mode,
–
–
The TRA bit indicates whether the master is in Receiver or Transmitter mode.
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until the first data byte is written into I2C_DR (see
sequencing EV8_1).
When the acknowledge pulse is received, the TxE bit is set by hardware and an interrupt is
generated if the ITEVFEN and ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared by a write to I2C_DR,
stretching SCL low.
Closing the communication
After the last byte is written to the DR register, the STOP bit is set by software to generate a
Stop condition (see
goes back to slave mode (MSL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
To enter Transmitter mode, a master sends the slave address with LSB reset.
To enter Receiver mode, a master sends the slave address with LSB set.
To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address, (where xx denotes the two most significant bits of the address).
To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address. Then it should send a repeated Start condition followed by the
header (11110xx1), (where xx denotes the two most significant bits of the
address).
Figure 242
Inter-integrated circuit (I
Transfer sequencing EV8_2). The interface automatically
RM0402 Rev 6
2
C) interface
Figure 242 Transfer
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