Table 64. Fsmc_Bcrx Bitfields (Muxed Mode); Figure 45. Muxed Write Access Waveforms - ST STM32F412 Reference Manual

RM0402
The difference with mode D is the drive of the lower address byte(s) on the data bus.
Bit number
31:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4

Figure 45. Muxed write access waveforms

A[25:16]
NADV
NEx
NOE
NWE
AD[15:0] Lower address
ADDSET
HCLK cycles

Table 64. FSMC_BCRx bitfields (Muxed mode)

Bit name
Reserved
WFDIS
CCLKEN
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
Reserved
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
Flexible static memory controller (FSMC)
Memory transaction
ADDHLD
HCLK cycles
0x000
As needed
As needed
0x0 (no effect in Asynchronous mode)
0x0 (no effect in Asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at 0.
0x0
0x0 (no effect in Asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
0x1
As needed
RM0402 Rev 6
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
MSv40112V2
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