Table 49. Nor Flash/Psram: Example Of Supported Memories; And Transactions - ST STM32F412 Reference Manual

Flexible static memory controller (FSMC)
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
PSRAM
(multiplexed
I/Os and non-
multiplexed
I/Os)
SRAM and
ROM
254/1163

Table 49. NOR Flash/PSRAM: example of supported memories

Mode R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous
R
page
Synchronous R
Synchronous R
Synchronous R
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous
R
page
Synchronous R
Synchronous R
Synchronous R
Synchronous W
Synchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
RM0402 Rev 6

and transactions

AHB Allowed/
Memory
data
data size
size allowed
8 16
8 16
16 16
16 16
32 16
32 16
- 16
8 16
16 16
32 16
8 16
8 16
16 16
16 16
32 16
32 16
- 16
8 16
16 16
32 16
8 16
16/32 16
8 / 16 16
8 / 16 16
32 16
32 16
not Comments
Y -
N -
Y -
Y -
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
N Mode is not supported
N -
Y -
Y -
Y -
Y Use of byte lanes NBL[1:0]
Y -
Y -
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
N Mode is not supported
N -
Y -
Y -
Y Use of byte lanes NBL[1:0]
Y -
Y -
Y Use of byte lanes NBL[1:0]
Y Split into 2 FSMC accesses
Split into 2 FSMC accesses
Y
Use of byte lanes NBL[1:0]
RM0402