Pll Configuration; Lse Clock - ST STM32F412 Reference Manual

RM0402
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
control register
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the
The HSIRDY flag in the
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
6.2.3

PLL configuration

The STM32F412xx devices feature two PLLs:
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
–
• A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality
audio performance on the I2S interface.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, P, Q and multiplication factor N).
The PLLI2S uses the same input clock as the main PLL (HSI or HSE). However, the PLLI2S
has dedicated enable/disable and division factors configuration bits. Refer to
RCC clock control register
(RCC_PLLCFGR)
(RCC_PLLI2SCFGR). Once the PLLI2S is enabled, the configuration parameters cannot be
changed.
The two PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock.
PLL configuration register (RCC_PLLCFGR)
(RCC_CFGR)
6.2.4

LSE clock

The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
(RCC_CR).
RCC clock control register
RCC clock control register (RCC_CR)
Section 6.2.7: Clock security system (CSS) on page
The first output is used to generate the high speed system clock (up to 100 MHz)
The second output is used to generate the clock for the USB OTG FS (48 MHz),
RNG and the SDIO (
≤
(RCC_CR),
and Section 6.3.23: RCC PLLI2S configuration register
can be used to configure PLL and PLLI2S, respectively.
Reset and clock control (RCC) for STM32F412xx
(RCC_CR).
50 MHz).
Section 6.3.2: RCC PLL configuration register
and RCC clock configuration register
RM0402 Rev 6
= 25 °C.
A
RCC clock
indicates if the HSI RC is
RCC clock control
116.
Section 6.3.1:
115/1163
RCC
166