Fmpi2C Control Register 2 (Fmpi2C_Cr2) - ST STM32F412 Reference Manual

RM0402
Bit 6 TCIE: Transfer Complete interrupt enable
Note: Any of these events generate an interrupt:
Bit 5 STOPIE: Stop detection Interrupt enable
Bit 4 NACKIE: Not acknowledge received Interrupt enable
Bit 3 ADDRIE: Address match Interrupt enable (slave only)
Bit 2 RXIE: RX Interrupt enable
Bit 1 TXIE: TX Interrupt enable
Bit 0 PE: Peripheral enable
Note: When PE=0, the FMPI2C SCL and SDA lines are released. Internal state machines and
23.7.2

FMPI2C control register 2 (FMPI2C_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
FMPI2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
HEAD1
NACK STOP START
rs rs rs
Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
Transfer Complete (TC)
Transfer Complete Reload (TCR)
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
0: Peripheral disable
1: Peripheral enable
status bits are put back to their reset value. When cleared, PE must be kept low for at
least 3 APB clock cycles.
28 27 26 25
PEC AUTOE
Res.
BYTE ND
rs rw
12 11 10 9
RD_
ADD10
0R WRN
rw rw rw rw
24 23 22
RE
LOAD
rw rw rw
8 7 6
rw rw rw
RM0402 Rev 6
21 20 19 18
NBYTES[7:0]
rw rw rw rw
5 4 3 2
SADD[9:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
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