Fmpi2C Block Diagram; Figure 208. Fmpi2C Block Diagram - ST STM32F412 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
23.4.1

FMPI2C block diagram

The block diagram of the FMPI2C interface is shown in
I2c_ker_ck
I2c_pclk
The FMPI2C is clocked by an independent clock source which allows the FMPI2C to
operate independently from the PCLK frequency.
For I2C I/Os supporting 20mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to
658/1163

Figure 208. FMPI2C block diagram

I2CCLK
Wakeup
on
address
match
PCLK
Section 23.3: FMPI2C
Data control
Digital
Shift register
noise
filter
SMBUS
PEC
generation/
check
Clock control
Master clock
Digital
generation
noise
Slave clock
filter
stretching
SMBus
Timeout
check
SMBus Alert
control &
status
Registers
APB bus
implementation.
RM0402 Rev 6
Figure 208.
Analog
noise
GPIO
filter
logic
Analog
noise
GPIO
filter
logic
RM0402
I2C_SDA
I2C_SCL
I2C_SMBA
MSv46198V2