Dma Transfer Suspension - ST STM32F412 Reference Manual

Direct memory access controller (DMA)
•
In Peripheral flow controller mode:
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Note: The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in non-circular mode, after the end of the transfer (that is when
the number of data to be transferred reaches zero), the DMA is stopped (EN bit in
DMA_SxCR register is cleared by Hardware) and no DMA request is served unless the
software reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR
register).
9.3.15

DMA transfer suspension

At any time, a DMA transfer can be suspended to be restarted later on or to be definitively
disabled before the end of the DMA transfer.
There are two cases:
• The stream disables the transfer with no later-on restart from the point where it was
stopped. There is no particular action to do, except to clear the EN bit in the
DMA_SxCR register to disable the stream. The stream may take time to be disabled
(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the
DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The
value of the EN bit in DMA_SxCR is now 0 to confirm the stream interruption. The
DMA_SxNDTR register contains the number of remaining data items at the moment
when the stream was stopped so that the software can determine how many data items
have been transferred before the stream was interrupted.
• The stream suspends the transfer before the number of remaining data items to be
transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer
later by re-enabling the stream. In order to restart from the point where the transfer was
stopped, the software has to read the DMA_SxNDTR register after disabling the stream
by writing the EN bit in DMA_SxCR register (and then checking that it is at 0) to know
the number of data items already collected. Then:
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–
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Note: A transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to indicate the
end of transfer due to the stream interruption.
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to-memory) all the remaining data have been flushed from the FIFO into the
memory.
The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
The stream is disabled by software, and (when the DMA is operating in peripheral-
to-memory mode) the remaining data have been transferred from the FIFO into
the memory
The peripheral and/or memory addresses have to be updated in order to adjust
the address pointers
The SxNDTR register has to be updated with the remaining number of data items
to be transferred (the value read when the stream was disabled)
The stream may then be re-enabled to restart the transfer from the point it was
stopped
RM0402 Rev 6
RM0402