Figure 351. Receive Fifo Packet Read - ST STM32F412 Reference Manual

RM0402
c)
d)
e)
5. After the data payload is popped from the receive FIFO, the RXFLVL interrupt
(OTG_GINTSTS) must be unmasked.
6. Steps 1–5 are repeated every time the application detects assertion of the interrupt line
due to RXFLVL in OTG_GINTSTS. Reading an empty receive FIFO can result in
undefined core behavior.
Figure 351
SETUP transactions
DPID = DATA0. These data indicate that a SETUP packet for the specified
endpoint is now available for reading from the receive FIFO.
Setup stage done pattern:
PKTSTS = Setup Stage Done, BCNT = 0x0, EPNUM = Control EP Num,
DPID = (0b00).
These data indicate that the setup stage for the specified endpoint has completed
and the data stage has started. After this entry is popped from the receive FIFO,
the core asserts a setup interrupt on the specified control OUT endpoint.
Data OUT packet pattern:
PKTSTS = DataOUT, BCNT = size of the received data OUT packet (0 ≤ BCNT
≤ 1 024), EPNUM = EPNUM on which the packet was received, DPID = Actual
Data PID.
Data transfer completed pattern:
PKTSTS = Data OUT transfer done, BCNT = 0x0, EPNUM = OUT EP Num on
which the data transfer is complete, DPID = (0b00).
These data indicate that an OUT data transfer for the specified OUT endpoint has
completed. After this entry is popped from the receive FIFO, the core asserts a
transfer completed interrupt on the specified OUT endpoint.
provides a flowchart of the above procedure.

Figure 351. Receive FIFO packet read

USB on-the-go full-speed (OTG_FS)
RM0402 Rev 6 1097/1163
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