Rtc Prescaler Register (Rtc_Prer) - ST STM32F412 Reference Manual

Real-time clock (RTC)
Bit 3 SHPF: Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR. It is cleared by hardware when the corresponding shift operation has been
executed. Writing to SHPF has no effect.
Bit 2 WUTWF: Wakeup timer write flag
This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in
RTC_CR. It is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The
wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
0: Wakeup timer configuration update not allowed
1: Wakeup timer configuration update allowed
Bit 1 ALRBWF: Alarm B write flag
This bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm B update not allowed
1: Alarm B update allowed.
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed
Note: The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming
them to 0.
This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure
is described in
22.6.5

RTC prescaler register (RTC_PRER)

Address offset: 0x10
Backup domain reset value: 0x007F 00FF
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
rw rw
640/1163
RTC register write
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
protection.
24 23 22
Res. Res.
rw
8 7 6
PREDIV_S[14:0]
rw rw rw
RM0402 Rev 6
21 20 19 18
PREDIV_A[6:0]
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0402
17 16
rw rw
1 0
rw rw