Multi-Master Communication; Slave Select (Nss) Pin Management; Figure 275. Multi-Master Application - ST STM32F412 Reference Manual

RM0402
26.3.4

Multi-master communication

Unless SPI bus is not designed for a multi-master capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.
If potentially both nodes raised their mastering request at the same time a bus conflict event
appears (see mode fault MODF event). Then the user can apply some simple arbitration
process (e.g. to postpone next attempt by predefined different time-outs applied at both
nodes).
Rx (Tx) shift register
Tx (Rx) shift register
1. The NSS pin is configured at hardware input mode at both nodes. Its active level enables the MISO line
output control as the passive node is configured as a slave.
26.3.5

Slave select (NSS) pin management

In slave mode, the NSS works as a standard "chip select" input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
•
Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.
• Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).

Figure 275. Multi-master application

SPI clock
generator
Master
(Slave)
RM0402 Rev 6
Serial peripheral interface/ inter-IC sound (SPI/I2S)
MISO MISO
MOSI
SCK
GPIO
(1)
NSS
Rx (Tx) shift register
MOSI
Tx (Rx) shift register
SCK
SPI clock
generator
(1)
NSS
Master
GPIO
(Slave)
MSv39628V1
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