Sdio Data Length Register (Sdio_Dlen); Sdio Data Control Register (Sdio_Dctrl) - ST STM32F412 Reference Manual

Secure digital input/output interface (SDIO)
27.8.8

SDIO data length register (SDIO_DLEN)

Address offset: 0x28
Reset value: 0x0000 0000
The SDIO_DLEN register contains the number of data bytes to be transferred. The value is
loaded into the data counter when data transfer starts.
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 24:0 DATALENGTH: Data length value
Number of data bytes to be transferred.
Note: For a block data transfer, the value in the data length register must be a multiple of the block
size (see SDMMC_DCTRL). Before being written to the data control register a timeout must
be written to the data timer register and the data length register.
In case of IO_RW_EXTENDED (CMD53):
- If the Stream or SDIO multibyte data transfer is selected the value in the data length
register must be between 1 and 512.
- If the Block data transfer is selected the value in the data length register must be between
1*Data block size and 512*Data block size.
27.8.9

SDIO data control register (SDIO_DCTRL)

Address offset: 0x2C
Reset value: 0x0000 0000
The SDIO_DCTRL register control the data path state machine (DPSM).
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
910/1163
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
SDIO RW RW
EN MOD STOP
rw rw rw
24 23 22
rw rw rw
8 7 6
DATALENGTH[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
RW
DBLOCKSIZE
START
rw rw rw
RM0402 Rev 6
21 20 19 18
DATALENGTH[24:16]
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DMA DT
EN MODE
rw rw rw rw
RM0402
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
DTDIR DTEN
rw rw