ST STM32F412 Reference Manual page 948

Controller area network (bxCAN)
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 RFOM0
Set by software to release the output mailbox of the FIFO. The output mailbox can only be
released when at least one message is pending in the FIFO. Setting this bit when the FIFO
is empty has no effect. If at least two messages are pending in the FIFO, the software has to
release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
Bit 4 FOVR0
This bit is set by hardware when a new message has been received and passed the filter
while the FIFO was full.
This bit is cleared by software.
Bit 3 FULL0
Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
Bit 2 Reserved, must be kept at reset value.
Bits 1:0 FMP0[1:0]
These bits indicate how many messages are pending in the receive FIFO.
FMP is increased each time the hardware stores a new message in to the FIFO. FMP is
decreased each time the software releases the output mailbox by setting the RFOM0 bit.
CAN receive FIFO 1 register (CAN_RF1R)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 RFOM1
Bit 4 FOVR1
948/1163
:
Release FIFO 0 output mailbox
:
FIFO 0 overrun
:
FIFO 0 full
:
FIFO 0 message pending
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
:
Release FIFO 1 output mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can only be
released when at least one message is pending in the FIFO. Setting this bit when the FIFO
is empty has no effect. If at least two messages are pending in the FIFO, the software has to
release the output mailbox to access the next message.
Cleared by hardware when the output mailbox has been released.
:
FIFO 1 overrun
This bit is set by hardware when a new message has been received and passed the filter
while the FIFO was full.
This bit is cleared by software.
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res. RFOM1 FOVR1 FULL1
RM0402 Rev 6
21 20 19 18
Res. Res. Res.
5 4 3 2
Res.
rs rc_w1 rc_w1
RM0402
17 16
Res. Res.
1 0
FMP1[1:0]
r r