29.15.55 Otg_Fs Register Map; Table 208. Otg_Fs Register Map And Reset Values - ST STM32F412 Reference Manual

RM0402
Bit 5 ENL1GTG: Enable sleep clock gating
Bit 4 PHYSUSP: PHY suspended
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
Bit 0 STPPCLK: Stop PHY clock

29.15.55 OTG_FS register map

The table below gives the USB OTG register map and reset values.
Register
Offset
name
OTG_
GOTGCTL
0x000
Reset value
OTG_
GOTGINT
0x004
Reset value
OTG_
GAHBCFG
0x008
Reset value
OTG_
GUSBCFG
0x00C
Reset value
OTG_
GRSTCTL
0x010
Reset value 1
When this bit is set, core internal clock gating is enabled in Sleep state if the core cannot
assert utmi_l1_suspend_n. When this bit is not set, the PHY clock is not gated in Sleep
state.
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit.
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.

Table 208. OTG_FS register map and reset values

0 0
USB on-the-go full-speed (OTG_FS)
0 0 0 0 0 1
0 0 0
RM0402 Rev 6
0 0 0 0 0 0 0 0
- 0 0
0 0
TRDT
0 1 0 1 0 0 1
TXFNUM
0 0 0 0 0 0
0 0 0 0 0
0
0
TOCAL
0 0 0
0 0 0 0
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