Figure 84. Counter Timing Diagram, Update Event When Arpe=0; Figure 85. Counter Timing Diagram, Update Event When Arpe=1 - ST STM32F412 Reference Manual

RM0402
Timerclock = CK_CNT
Update interrupt flag (UIF)
Auto-reload preload register
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload shadow
Write a new value in TIMx_ARR

Figure 84. Counter timing diagram, update event when ARPE=0

CK_PSC
CEN
31
Counter register
Counter overflow
Update event (UEV)
FF
Write a new value in TIMx_ARR

Figure 85. Counter timing diagram, update event when ARPE=1

CK_PSC
CEN
F0
(UIF)
F5
register
register
Advanced-control timers (TIM1&TIM8)
(TIMx_ARR not preloaded)
32 33 34 35 36
(TIMx_ARR preloaded)
F1 F2 F3 F4 F5
F5
RM0402 Rev 6
00 01 03 04 05
02
36
00 01 02 03 04 05 06 07
36
36
06 07
MS31082V3
MS31083V2
419/1163
483