Fmpi2C Pec Register (Fmpi2C_Pecr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Bit 10 OVRCF: Overrun/Underrun flag clear

Bit 9 ARLOCF: Arbitration lost flag clear

Bit 8 BERRCF: Bus error flag clear

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 STOPCF: STOP detection flag clear

Bit 4 NACKCF: Not Acknowledge flag clear

Bit 3 ADDRCF: Address matched flag clear

Bits 2:0 Reserved, must be kept at reset value.

FMPI2C PEC register (FMPI2C_PECR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: No wait states

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0] Packet error checking register

If the SMBus feature is not supported, this register is reserved and forced by hardware to

"0x00000000". Refer to

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register.

Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register.

Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.

Writing 1 to this bit clears the STOPF flag in the FMPI2C_ISR register.

Writing 1 to this bit clears the NACKF flag in FMPI2C_ISR register.

Writing 1 to this bit clears the ADDR flag in the FMPI2C_ISR register. Writing 1 to this bit

also clears the START bit in the FMPI2C_CR2 register.

This field contains the internal PEC when PECEN=1.

The PEC is cleared by hardware when PE=0.

Section 23.3: FMPI2C

implementation.

RM0402 Rev 6

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