Figure 88. Counter Timing Diagram, Internal Clock Divided By 4; Figure 89. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F412 Reference Manual

Advanced-control timers (TIM1&TIM8) RM0402

Figure 88. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
0001 0000 0000 0001
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31186V1

Figure 89. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
20 1F 00 36
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
(UIF)
MS31187V1
422/1163 RM0402 Rev 6