Rcc Clocks Gated Enable Register (Ckgatenr) - ST STM32F412 Reference Manual

Reset and clock control (RCC) for STM32F412xx
Bits 23: 16 Reserved, must be kept at reset value.
Bit 15 CKDFSDM1ASEL: DFSDM1 audio clock selection.
Bits 14:0 Reserved, must be kept at reset value.
6.3.25

RCC clocks gated enable register (CKGATENR)

Address offset: 0x90
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to enable or disable the clock gating for the specified IPs.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 EVTCL_CKEN
Bit 6 RCC_CKEN: RCC clock enable
Bit 5 FLITF_CKEN: Flash Interface clock enable
Bit 4 SRAM_CKEN: SRQAM controller clock enable
Bit 3 SPARE_CKEN: Spare clock enable
162/1163
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
0: the clock gating is enabled
1: the cock gating is disabled, the clock is always enabled
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
EVTCL RCC FLITF SRAM
_CKEN _CKEN _CKEN _CKEN
rw rw rw rw
RM0402 Rev 6
19 18 17
Res. Res. Res.
3 2 1
SPARE CM4DBG AHB2APB2
_CKEN _CKEN _CKEN
rw rw rw
RM0402
16
Res.
0
AHB2APB1
_CKEN
rw