Procedure For Disabling The Spi; Figure 279. Txe/Rxne/Bsy Behavior In Slave / Full-Duplex Mode (Bidimode=0, Rxonly=0) In The Case Of Continuous Transfers - ST STM32F412 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
Figure 279. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
Example in Slave mode with CPOL=1, CPHA=1
SCK
MISO/MOSI (out)
TXE flag
Tx buffer
(write to SPI_DR)
BSY flag
MISO/MOSI (in)
RXNE flag
Rx buffer
(read from SPI_DR)
software software waits
writes 0xF1 until TXE=1 and
into SPI_DR writes 0xF2 into
SPI_DR
26.3.10

Procedure for disabling the SPI

When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Standard disable procedure is based on pulling BSY status together with TXE flag to check
if a transmission session is fully completed. This check can be done in specific cases, too,
when it is necessary to identify the end of ongoing transactions, for example:
•
When NSS signal is managed by an arbitrary GPIO toggle and the master has to
provide proper end of NSS pulse for slave, or
•
When transactions' streams from DMA are completed while the last data frame or CRC
frame transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive-only mode is used):
1. Wait until RXNE=1 to receive the last data.
2. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
3. Read received data.
826/1163
RXONLY=0) in the case of continuous transfers
DATA 1 = 0xF1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
cleared by software
0xF1 0xF2
set by cleared by software
DATA 1 = 0xA1
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
set by hardware
software waits software waits
until RXNE=1 until TXE=1 and
and reads 0xA1 writes 0xF3 into
from SPI_DR
RM0402 Rev 6
DATA 2 = 0xF2
set by hardware
cleared by software
0xF3
DATA 2 = 0xA2
cleared by software
0xA1
software waits
until RXNE=1
and reads 0xA2
SPI_DR from SPI_ DR
DATA 3 = 0xF3
set by hardware
reset by hardware
DATA 3 = 0xA3
0xA2
software waits
until RXNE=1
and reads 0xA3
from SPI_DR
RM0402
0xA3
ai17344