Sending The Instruction Only Once; Quadspi Error Management; Quadspi Busy Bit And Abort Functionality - ST STM32F412 Reference Manual

Quad-SPI interface (QUADSPI)
In case of match, the status match flag is set and an interrupt is generated if enabled, and
the QUADSPI can be automatically stopped if the AMPS bit is set.
In any case, the latest retrieved value is available in the QUADSPI_DR.
Memory-mapped mode
In memory-mapped mode, the external Flash memory is seen as internal memory but with
some latency during accesses. Only read operations are allowed to the external Flash
memory in this mode.
Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR
register.
The programmed instruction and frame is sent when a master is accessing the memory
mapped space.
The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to
QUADSPI_DR in this mode returns zero.
The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode.
12.3.12

Sending the instruction only once

Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be
sent only with the first command sequence, while subsequent commands start directly with
the address. One can take advantage of such a feature using the SIOO bit
(QUADSPI_CCR[28]).
SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If
the SIOO bit is set, the instruction is sent only for the first command following a write to
QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is
a write to QUADSPI_CCR.
SIOO has no effect when IMODE = 00 (no instruction).
12.3.13

QUADSPI error management

An error can be generated in the following case:
•
In indirect mode or status flag polling mode when a wrong address is programmed in
the QUADSPI_AR (according to the Flash memory size defined by FSIZE[4:0] in the
QUADSPI_DCR): this sets the TEF and an interrupt is generated if enabled.
•
Also in indirect mode, if the address plus the data length exceeds the Flash memory
size, TEF is set as soon as the access is triggered.
• In memory-mapped mode, when an out of range access is done by a master or when
the QUADSPI is disabled: this generates a bus error as a response to the faulty bus
master request.
•
When a master is accessing the memory mapped space while the memory mapped
mode is disabled: this generates a bus error as a response to the faulty bus master
request.
12.3.14

QUADSPI busy bit and abort functionality

Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is
automatically set in the QUADSPI_SR.
300/1163 RM0402 Rev 6
RM0402