Rng Status Register (Rng_Sr) - ST STM32F412 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

True random number generator (RNG)

RNG status register (RNG_SR)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 SEIS: Seed error interrupt status

Bit 5 CEIS: Clock error interrupt status

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 SECS: Seed error current status

Bit 1 CECS: Clock error current status

Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.

Bit 0 DRDY: Data Ready

This bit is set at the same time as SECS. It is cleared by writing 0. Writing 1 has no effect.

0: No faulty sequence detected

1: At least one faulty sequence has been detected. See SECS bit description for details.

An interrupt is pending if IE = 1 in the RNG_CR register.

This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect.

0: The RNG clock is correct (fRNGCLK > fHCLK/16)

1: The RNG has been detected too slow (fRNGCLK < fHCLK/16)

An interrupt is pending if IE = 1 in the RNG_CR register.

0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a

faulty sequence was detected and the situation has been recovered.

1: One of the noise source has provided more than 64 consecutive bits at a constant value

("0" or "1"), or more than 32 consecutive occurrence of two bits patterns ("01" or "10")

0: The RNG clock is correct (fRNGCLK> fHCLK/16). If the CEIS bit is set, this means that a

slow clock was detected and the situation has been recovered.

1: The RNG clock is too slow (fRNGCLK< fHCLK/16).

0: The RNG_DR register is not yet valid, no random data is available.

1: The RNG_DR register contains valid random data.

Once the RNG_DR register has been read, this bit returns to 0 until a new random value is

If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1.

RM0402 Rev 6

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