RM0402
2
26.6
I
S functional description
2
26.6.1
I
S general description
The block diagram of the I
MOSI/SD
MISO/
I2S2ext_SD/
I2S3ext_SD (1)
NSS/WS
CK
I2SMOD
MCK
1. I2S2ext_SD and I2S3ext_SD are the extended SD pins that control the I2S full-duplex mode.
2. MCK is mapped on the MISO pin.
2
S is shown in
Figure 283. I
Master control logic
SPI
baud rate generator
I2S_ CK
RM0402 Rev 6
Serial peripheral interface/ inter-IC sound (SPI/I2S)
Figure
283.
2
S block diagram
Address and data bus
Tx buffer
BSY OVR MODF
16-bit
Shift register
16-bit
Rx buffer
I2SCFG
I2SSTD
[1:0]
[1:0]
Bidi
Bidi
mode
OE
LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
First
2
I
S clock generator
MCKOE
ODD
I2SDIV[7:0]
CRC
CH
UDR
TxE RxNE
ERR
SIDE
LSB first
Communication
CK
CH
DATLEN
LEN
[1:0]
POL
I2S
MOD I2SE
CRC
CRC
Rx
DFF
SSM SSI
EN
Next
only
I2SxCLK
FRE
control
MS19909V1
835/1163
862
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