Table 166. Dpsm Flags - ST STM32F412 Reference Manual

Secure digital input/output interface (SDIO)
DPSM Flags
The status of the data path subunit transfer is reported by several status flags
Flag
DBCKEND
DATAEND
DTIMEOUT
DCRCFAIL
Data FIFO
The data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.
The FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic.
Because the data FIFO operates in the APB2 clock domain (PCLK2), all signals from the
subunits in the SDIO clock domain (SDIOCLK) are resynchronized.
Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or
receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually
exclusive:
–
–
•
Transmit FIFO:
Data can be written to the transmit FIFO through the APB2 interface when the SDIO is
enabled for transmission.
The transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO
contains a data output register that holds the data word pointed to by the read pointer.
When the data path subunit has loaded its shift register, it increments the read pointer
and drives new data out.
If the transmit FIFO is disabled, all status flags are deasserted. The data path subunit
asserts TXACT when it transmits data.
876/1163
Set to high when data block send/receive CRC check is passed.
In SDIO multibyte transfer mode this flag is set at the end of the transfer (a
multibyte transfer is considered as a single block transfer by the host).
Set to high when SDIO_DCOUNT register decrements and reaches 0.
DATAEND indicates the end of a transfer on SDIO data line.
Set to high when data timeout period is reached.
When data timer reaches zero while DPSM is in Wait_R or Busy state, timeout is
set. DTIMEOUT can be set after DATAEND if DPSM remains in busy state for
longer than the programmed period.
Set to high when data block send/receive CRC check fails.
The transmit FIFO refers to the transmit logic and data buffer when TXACT is
asserted
The receive FIFO refers to the receive logic and data buffer when RXACT is
asserted

Table 166. DPSM flags

Description
RM0402 Rev 6
RM0402