Single And Burst Transfers; Table 34. Packing/Unpacking And Endian Behavior (Bit Pinc = Minc = 1); Table 35. Restriction On Ndt Versus Psize And Msize - ST STM32F412 Reference Manual

RM0402

Table 34. Packing/unpacking and endian behavior (bit PINC = MINC = 1)

Number
AHB AHB
memory peripheral
items to
port port
transfer
width width
8 8
8 16
8 32
16 8
16 16
16 32
32 8
32 16
32 32
Note: Peripheral port may be the source or the destination (it can also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] must be configured so as to ensure that the last transfer is
not incomplete. This can occur when the data width of the peripheral port (PSIZE bits) is
lower than the data width of the memory port (MSIZE bits). This constraint is summarized in
the table below.
PSIZE[1:0] of DMA_SxCR
9.3.12

Single and burst transfers

The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or
16 beats.
-
of data Memory Memory port
transfer address / byte
-
number
(NDT)
1 0x0 / B0[7:0]
2 0x1 / B1[7:0]
-
4
3 0x2 / B2[7:0]
4 0x3 / B3[7:0]
1 0x0 / B0[7:0]
2 0x1 / B1[7:0]
-
2
3 0x2 / B2[7:0]
4 0x3 / B3[7:0]
1 0x0 / B0[7:0]
2 0x1 / B1[7:0]
-
1
3 0x2 / B2[7:0]
4 0x3 / B3[7:0]
1 0x0 / B1|B0[15:0]
2 0x2 / B3|B2[15:0]
-
4
1 0x0 / B1|B0[15:0]
-
2
2 0x2 / B1|B0[15:0]
1 0x0 / B1|B0[15:0]
-
1
2 0x2 / B3|B2[15:0]
1 0x0 / B3|B2|B1|B0[31:0]
-
4
1 0x0 /B3|B2|B1|B0[31:0]
-
2
1 0x0 /B3|B2|B1|B0 [31:0]
-
1

Table 35. Restriction on NDT versus PSIZE and MSIZE

MSIZE[1:0] of DMA_SxCR
00 (8-bit)
00 (8-bit)
01 (16-bit)
Direct memory access controller (DMA)
Peripheral
transfer
lane number
1
2
3
4
1
2
1
1
2
3
4
1
2
1
1
2
3
4
1
2
1
01 (16-bit)
10 (32-bit)
10 (32-bit)
RM0402 Rev 6
Peripheral port address / byte lane
PINCOS = 1 PINCOS = 0
0x0 / B0[7:0] 0x0 / B0[7:0]
0x4 / B1[7:0] 0x1 / B1[7:0]
0x8 / B2[7:0] 0x2 / B2[7:0]
0xC / B3[7:0] 0x3 / B3[7:0]
0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]
0x0 / 0x0 /
B3|B2|B1|B0[31:0] B3|B2|B1|B0[31:0]
0x0 / B0[7:0] 0x0 / B0[7:0]
0x4 / B1[7:0] 0x1 / B1[7:0]
0x8 / B2[7:0] 0x2 / B2[7:0]
0xC / B3[7:0] 0x3 / B3[7:0]
0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]
0x0 / 0x0 /
B3|B2|B1|B0[31:0] B3|B2|B1|B0[31:0]
0x0 / B0[7:0] 0x0 / B0[7:0]
0x4 / B1[7:0] 0x1 / B1[7:0]
0x8 / B2[7:0] 0x2 / B2[7:0]
0xC / B3[7:0] 0x3 / B3[7:0]
0x0 / B1|B0[15:0] 0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0] 0x2 / B3|B2[15:0]
0x0 / 0x0 /
B3|B2|B1|B0 [31:0] B3|B2|B1|B0[31:0]
NDT[15:0] of DMA_SxNDTR
Must be a multiple of 2.
Must be a multiple of 4.
Must be a multiple of 2.
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