ST STM32F412 Reference Manual page 196

Direct memory access controller (DMA)
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Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
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Incrementing or non-incrementing addressing for source and destination
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Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
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Each stream supports circular buffer management
• 5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA
FIFO error, direct mode error) logically ORed together in a single interrupt request for
each stream
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DMA flow controller: the number of data items to be transferred is software-
programmable from 1 to 65535
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
RM0402 Rev 6
RM0402